HDLbits exercises 6 (MULTIPLEXERS节选题)

目录

1\ MUX9TO1V

2\ MUX256TO1

3\ MUX256TO1V

---

1\ MUX9TO1V

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

CORRECT:

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out ); 
    always@(*)
        begin
            case(sel)
                4'b0000:out=a;
                4'b0001:out=b;
                4'b0010:out=c;
                4'b0011:out=d;
                4'b0100:out=e;
                4'b0101:out=f;
                4'b0110:out=g;
                4'b0111:out=h;
                4'b1000:out=i;
                4'b1001:out=16'hffff;
                4'b1010:out=16'hffff;
                4'b1011:out=16'hffff;
                4'b1100:out=16'hffff;
                4'b1101:out=16'hffff;
                4'b1110:out=16'hffff;
                4'b1111:out=16'hffff;
                default:out=16'hffff;
            endcase
        end  
endmodule

CORRECT2:

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*)
        begin
            case(sel)
                4'b0000:out=a;
                4'b0001:out=b;
                4'b0010:out=c;
                4'b0011:out=d;
                4'b0100:out=e;
                4'b0101:out=f;
                4'b0110:out=g;
                4'b0111:out=h;
                4'b1000:out=i;
                default:out=16'hffff;
            endcase
        end
endmodule

CORRECT3:

module top_module (
    input [15:0] a,
    input [15:0] b,
    input [15:0] c,
    input [15:0] d,
    input [15:0] e,
    input [15:0] f,
    input [15:0] g,
    input [15:0] h,
    input [15:0] i,
    input [3:0] sel,
    output logic [15:0] out
);

    // Case statements can only be used inside procedural blocks (always block)
    // This is a combinational circuit, so use a combinational always @(*) block.
    always @(*) begin
        out = '1;        // '1 is a special literal syntax for a number with all bits set to 1.
                        // '0, 'x, and 'z are also valid.
                        // I prefer to assign a default value to 'out' instead of using a
                        // default case.
        case (sel)
            4'h0: out = a;
            4'h1: out = b;
            4'h2: out = c;
            4'h3: out = d;
            4'h4: out = e;
            4'h5: out = f;
            4'h6: out = g;
            4'h7: out = h;
            4'h8: out = i;
        endcase
    end   
endmodule

2\ MUX256TO1

Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

HINT:

• With this many options, a case statement isn't so useful.
• Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. In particular, selecting one bit out of a vector using a variable index will work.

CORRECT:

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out=in[sel];    //让sel信号当可变信号，跟函数中的自变量相似。
endmodule

3\ MUX256TO1V

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

HINT:

• With this many options, a case statement isn't so useful.
• Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. It's not always good at this. An error saying "... is not a constant" means it couldn't prove that the select width is constant. In particular, in[ sel*4+3 : sel*4 ] does not work.
• Bit slicing ("Indexed vector part select", since Verilog-2001) has an even more compact syntax.

ERRO:

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out = in[sel*4+3:sel*4];  //此时会报错，因为该等式不能证明选择的这个位宽是个常数。所以我们继续按bit进行选取然后进行拼接。要保证选择的位宽是常数。
endmodule

CORRECT:

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out= {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};
endmodule