Sequential Logic

Latches and Flip-Flops

• D flip-flop

  题目链接

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always @ (posedge clk) begin
        q <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12

• D flip-flops

  题目链接

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always @ (posedge clk) begin
        q <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9

• DFF with reset

  题目链接

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @ (posedge clk) begin
        if (reset)
        	q <= 0;
        else
            q <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13

• DFF with reset value

  题目链接

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always @ (negedge clk) begin
        if (reset)
            q <= 8'h34;
        else
            q <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13

• DFF with asynchronous reset

  题目链接

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @ (posedge clk or posedge areset) begin
        if (areset)
            q <= 0;
        else
            q <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13

• DFF with byte enable

  题目链接

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always @ (posedge clk) begin
        if (~resetn) begin
            q <= 16'b0;
        end
        else begin
            q <= {(({8{byteena[1]}} & d[15:8]) | ({8{~byteena[1]}} & q[15:8])), (({8{byteena[0]}} & d[7:0]) | ({8{~byteena[0]}} & q[7:0]))};
        end
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

• D Latch

  题目链接

module top_module (
    input d, 
    input ena,
    output q);
    reg q_reg;
    assign q = q_reg;
    always @ (*) begin
        if (ena)
            q_reg <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11

• DFF

  题目链接

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    always @ (posedge clk or posedge ar) begin
        if (ar) 
            q <= 0;
        else
        	q <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12

• DFF

  题目链接

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    always @ (posedge clk) begin
        if (r) begin
            q <= 0;
        end
        else begin
            q <= d;
        end
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14

• DFF + Gate

  题目链接

module top_module (
    input clk,
    input in, 
    output out);
    always @ (posedge clk) begin
        out <= (in ^ out); 
    end
endmodule
1
2
3
4
5
6
7
8

• Mux and DFF

  题目链接

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    wire ff_in = L ? r_in : q_in;
    always @ (posedge clk) begin
        Q <= ff_in;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11

• Mux and DFF

  题目链接

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
	wire ff_in_1 = E ? w : Q;
    wire ff_in = L ? R : ff_in_1;
    always @ (posedge clk) begin
       Q <= ff_in; 
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11

• DFFs and gates

  题目链接

module top_module (
    input clk,
    input x,
    output z
); 
    reg Q_ff1 = 0, Q_ff2 = 0, Q_ff3 = 0;
    wire D_ff1, D_ff2, D_ff3;
    assign D_ff1 = x ^ Q_ff1;
    assign D_ff2 = ~Q_ff2 & x;
    assign D_ff3 = ~Q_ff3 | x;
    assign z = ~(Q_ff1 | Q_ff2 | Q_ff3);
    always @ (posedge clk) begin
        Q_ff1 <= D_ff1;
        Q_ff2 <= D_ff2;
        Q_ff3 <= D_ff3;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

• Create circuit from truth table

  题目链接

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    reg Q_old;
    always @ (posedge clk) begin
        case({j,k})
            2'b00: Q <= Q_old;
            2'b01: Q <= 0;
            2'b10: Q <= 1;
            2'b11: Q <= ~Q_old;
        endcase
    end
    
    always @ (*) begin
        Q_old <= Q;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

• Detect an edge

  题目链接

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] in_old = 8'b0;
    always @ (posedge clk) begin
        pedge <= (in & ~in_old);
        in_old <= in;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11

• Detect both edges

  题目链接

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0] in_old;
    always @ (posedge clk) begin
        anyedge <= in_old ^ in;
        in_old <= in;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11

• Edge capture register

  题目链接

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out = 32'b0
);
    reg [31:0] in_old = 32'b0;
    //reg reset_old = 0;
    reg [31:0] out_last = 32'b0;
    always @ (posedge clk) begin
        if (reset) begin
            out <= 'b0;
        end
        else begin
            out <= (in_old & ~in) | out_last;
        end
        in_old <= in;
    end
    
    always @ (*) begin
        out_last <= out;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

• Edge capture register

  题目链接

module top_module (
    input clk,
    input d,
    output q
);
    reg q_1, q_2;
    assign q = clk ? q_1 : q_2;
    always @ (posedge clk) begin
        q_1 <= d;
    end
    always @ (negedge clk) begin
        q_2 <= d;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Counters

• Four-bit binary counter

  题目链接

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    
    always @ (posedge clk) begin
        q = ({q + 1} % 16) & {4{~reset}};
    end
endmodule

1
2
3
4
5
6
7
8
9
10

• Decade counter

  题目链接

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
	always @ (posedge clk) begin
        q <= ({q + 1} % 10) & {4{~reset}};
    end
endmodule
1
2
3
4
5
6
7
8

• Decade counter again

  题目链接

module top_module (
    input clk,
    input reset,
    output [3:0] q);
	always @ (posedge clk) begin
        q <= ((q % 10 + 1) & {4{~reset}}) | ((4'b1) & {4{reset}});
    end
endmodule
1
2
3
4
5
6
7
8

• Slow decade counter

  题目链接

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    reg [3:0] q_last;
    always @ (posedge clk) begin
        case({reset, slowena})
            2'b00: q <= q_last;
            2'b01: q <= {q_last + 1} % 10;
            2'b10: q <= 0;
            2'b11: q <= 0;
        endcase
    end
    
    always @ (*) begin
        q_last <= q;
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

• Counter 1-12

  题目链接

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
    assign c_enable = enable;
    assign c_load = (reset | (enable & Q==12)) ? 1 : 0;
    assign c_d = 4'b1;
    count4 the_counter (clk, c_enable, c_load, c_d, Q /*, ... */ );
endmodule

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

• Counter 1000

  题目链接

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    reg [3:0] Q[2:0];
    reg [3:0] Q_last[2:0];
    assign c_enable[0] = 1;
    assign c_enable[1] = (Q[0] == 4'b1001 && Q_last[0] == 4'b1000) ? 1 : 0;
    assign c_enable[2] = (Q[1] == 4'b1001 && Q[0] == 4'b1001 && Q_last[0] == 4'b1000) ? 1 : 0;
    assign OneHertz    = (Q[2] == 4'b1001 && Q[1] == 4'b1001 && Q[0] == 4'b1001 && Q_last[0] == 4'b1000) ? 1 : 0;
    bcdcount counter0 (clk, reset, c_enable[0], Q[0]/*, ... */);
    bcdcount counter1 (clk, reset, c_enable[1], Q[1]/*, ... */);
    bcdcount counter2 (clk, reset, c_enable[2], Q[2]/*, ... */);
    always @ (posedge clk) begin
        Q_last[2:0] <= Q[2:0]; 
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

• 4-digit decimal clock

  题目链接

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    assign ena[1] = (q[3:0]==4'd9);
    assign ena[2] = (ena[1] & q[7:4]==4'd9);
    assign ena[3] = (ena[2] & q[11:8]==4'd9);
    
    always @ (posedge clk) begin
        if(reset) begin
            q <= 'b0;
        end
        else begin
            case ({ena[1], ena[2], ena[3]})
                3'b100: begin q[3:0] <= 0; q[7:4] <= q[7:4] + 1; end
                3'b110: begin q[3:0] <= 0; q[7:4] <= 0; q[11:8] <= q[11:8] + 1; end
                3'b111: begin q[3:0] <= 0; q[7:4] <= 0; q[11:8] <= 0; q[15:12] <= {q[15:12] + 1} % 10; end
                default: begin q[3:0] <= q[3:0]  + 1; end
            endcase
        end
        
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

• 12-hour clock

  题目链接

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    wire ss_3_0_inc = (ss[3:0] == 4'd9) ? 1 : 0;
    wire ss_7_4_inc = (ss[7:4] == 4'd5 & ss_3_0_inc) ? 1 : 0;
    wire mm_3_0_inc = (mm[3:0] == 4'd9 & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
    wire mm_7_4_inc = (mm[7:4] == 4'd5 & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
    wire hh_3_0_inc = (hh[3:0] == 4'd9 & mm_7_4_inc & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
    wire hh_7_4_inc = (hh[7:4] == 4'd1 & hh[3:0] == 4'd2 & mm_7_4_inc & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
    wire pm_rev = (hh[7:4] == 4'd1 & hh[3:0] == 4'd1 & mm_7_4_inc & mm_3_0_inc & ss_7_4_inc & ss_3_0_inc) ? 1 : 0;
    
    always @ (posedge clk) begin
        if (reset) begin
            hh[7:4] <= 'd1;
            hh[3:0] <= 'd2;
            mm[7:4] <= 'd0;
            mm[3:0] <= 'd0;
            ss[7:4] <= 'd0;
            ss[3:0] <= 'd0;
            pm <= 0;
        end
        else begin
            if (pm_rev)
            	pm <= ~pm;
            if (ena) begin
                case ({hh_7_4_inc,hh_3_0_inc,mm_7_4_inc,mm_3_0_inc,ss_7_4_inc,ss_3_0_inc})
                    'b000001: begin 
                        ss[3:0] <= 0; ss[7:4] <= ss[7:4] + 1; 
                    end
                    'b000011: begin 
                        ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= mm[3:0] + 1; 
                    end
                    'b000111: begin 
                        ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= mm[7:4] + 1; 
                    end
                    'b001111: begin 
                        ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= 0; hh[3:0] <= hh[3:0] + 1; 
                    end
                    'b011111: begin 
                        ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= 0; hh[3:0] <= 0; hh[7:4] <= hh[7:4] + 1; 
                    end
                    'b101111: begin 
                        ss[3:0] <= 0; ss[7:4] <= 0; mm[3:0] <= 0; mm[7:4] <= 0; hh[3:0] <= 1; hh[7:4] <= 0; 
                    end
                    default: begin
                        ss[3:0] <= ss[3:0] + 1;
                    end
                endcase
                
            end
        end
    end
endmodule
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

## Shift Registers ## More Circuits ## Finite State Machines