• HDLbits:Lemmings4


    这道题目并不难,我想的太难了。只需要在前一道题目的基础上做下面几个步骤:

    1、lemming多加一个状态DEAD

    2、加一个always块记录下落时间

    3、把这个下落时间引入到FALLING落地状态转换的判断里

    PS:容易出错的地方:1、计数器到达19是完整的20s时间 2、不仅重置的时候计数器需要清零,除了下落之外的其他状态也要清零。

    1. module top_module(
    2. input clk,
    3. input areset, // Freshly brainwashed Lemmings walk left.
    4. input bump_left,
    5. input bump_right,
    6. input ground,
    7. input dig,
    8. output walk_left,
    9. output walk_right,
    10. output aaah,
    11. output digging );
    12. parameter LEFT=7'b0000001, RIGHT=7'b0000010, LEFT_FALLING=7'b0000100, RIGHT_FALLING=7'b0001000,
    13. LEFT_DIGGING=7'b0010000, RIGHT_DIGGING=7'b0100000, DEAD=7'b1000000, DEAD_TIME=32'd19;
    14. reg [6:0] state,next_state;
    15. reg [31:0] falltime_counter;
    16. always@(*)begin
    17. case(state)
    18. LEFT: next_state = ground?(dig?LEFT_DIGGING:(bump_left?RIGHT:LEFT)):LEFT_FALLING;
    19. RIGHT: next_state = ground?(dig?RIGHT_DIGGING:(bump_right?LEFT:RIGHT)):RIGHT_FALLING;
    20. LEFT_FALLING: next_state = ground?(falltime_counter>DEAD_TIME?DEAD:LEFT):LEFT_FALLING;
    21. RIGHT_FALLING: next_state = ground?(falltime_counter>DEAD_TIME?DEAD:RIGHT):RIGHT_FALLING;
    22. LEFT_DIGGING: next_state = ground?LEFT_DIGGING:LEFT_FALLING;
    23. RIGHT_DIGGING: next_state = ground?RIGHT_DIGGING:RIGHT_FALLING;
    24. DEAD: next_state = DEAD;
    25. default: next_state = LEFT;
    26. endcase
    27. end
    28. always@(posedge clk or posedge areset)begin
    29. if(areset)
    30. state <= LEFT;
    31. else
    32. state <= next_state;
    33. end
    34. always@(posedge clk or posedge areset )begin
    35. if(areset)
    36. falltime_counter <= 0;
    37. else if(state == RIGHT_FALLING || state == LEFT_FALLING)
    38. falltime_counter <= falltime_counter + 1;
    39. else
    40. falltime_counter <= 0;
    41. end
    42. assign walk_left = (state == LEFT);
    43. assign walk_right = (state == RIGHT);
    44. assign aaah = (state == LEFT_FALLING || state == RIGHT_FALLING);
    45. assign digging = (state == RIGHT_DIGGING || state == LEFT_DIGGING);
    46. endmodule

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  • 原文地址:https://blog.csdn.net/weixin_41004238/article/details/133818933