【Verilog】除2，正负数

在Verilog中，我们会用移位来表示除2的操作，但是负数的存在，我们就不得直接移位，是需要特殊处理的。

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/09/09 14:49:03
// Design Name: 
// Module Name: tb_divide_2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module tb_divide_2();

reg clk,rst;   
initial begin
    clk=0;
    forever #4.545 clk=~clk;
end
initial begin
    rst=1;
    #9.09 rst=0;
end
//
// cnts
reg [7:0] cnts;
always @ (posedge clk or posedge rst)
begin
	if(rst)
	begin
	cnts <= 8'd0;
	end
	
	else
	begin
	cnts <=  cnts + 1'b1;
	end
end

reg [11:0] A,B,C;

// 
always @ (posedge clk or posedge rst)
begin
	if(rst)
	begin
	A<=12'd10;
	B<=-12'd10;
	C<=12'd0;
	end
	
	else
	begin
	case(cnts)
	8'd1:begin  C<=A>>1; end    
    8'd2:begin  C<=B>>1;  end    
    8'd3:begin  C<={A[11],A[11:1]};  end    
    8'd4:begin  C<={B[11],B[11:1]};  end    
	default:begin A<=A;B<=B;C<=C; end
	endcase
	end
end



endmodule

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