spyglass 学习笔记之cdc check

和lint check一样添加文件，goal 选择 cdc check

下面研究sdc书写

CDC setup 可以通过以下流程

建立SpyGlass CDC设置：

将时钟生成模块指定为black box

为设计指定时钟和复位

使用设置管理器 将时钟生成模块指定为black box

对时钟生成模块(比如PLL)的内部执行SpyGlass CDC分析非常复杂，而且对整体SpyGlass CDC分析几乎没有价值。将这些块标记为黑盒子，除非你有详细的SGDC约束来定义这些模块的时钟特性

标记PLL时钟生成模块为black boxes的方法是，在project file中设置如下命令： clock -name "clk_sys" reset -name "rst_n" -value 0 Timing Constrain

按照它们的用途，大致分为以下几类：

• （1）描述芯片的工作速度，即时钟的频率，包括create_clock,create_generated_clock等
• （2）描述芯片的边界约束，包括set_input_delay, set_output_delay等
• （3）描述芯片的一些设计违反rule（DRV），包括set_max_fanout,set_max_capacitance, set_max_transition等
• （4）描述设计中一些特殊的路径，包括set_false_path,set_multicycle_path等
• （5）描述设计中一些需要禁止的timing

大致常用sdc如下：

clock相关：

• create_clock     创建基本源时钟
• create_generated_clock
• set_clock_uncertaint
• set_clock_groups
• set_input_delay
• set_output_delay

系统接口相关：

• set_input_transition
• set_load set_driving_cell

时序特例相关：

• set_false_path
• set_multicycle_path

逻辑赋值相关：

• set_case_analysis

---

研究sdc书写转sgdc规律：

########################################################################
#Section 1: List of source clocks
#These clocks have set_false_path/set_clock_groups/set_clock_uncertainty associated with them

• eg:clock  -name "A2D_SYS_CLK"  -domain d0  -edge { "0.000000" "12.500000"}  -period 25 -tag cc_osc_clk 

########################################################################
#Section 2: List of remaining source clocks
#These clocks do not have the set_false_path/set_clock_groups/set_clock_uncertainty constraints associated with them

########################################################################
#Section 3: List of generated clocks
#These clocks satisfy either of the following conditions
 #a. Generated clocks have domains different than the domains of their source clocks
 #b. Generated clocks are specified on the black-boxe

########################################################################
#Section 4: List of generated clocks which have same domain as that of their source clock

########################################################################
#Section 5: List of valid set_case_analyis constraint generated from set_case_analysis command.

• eg:set_case_analysis -name "ggggggg_digital.u_inf_clk.esd_sram_recover_clken" -value 0

########################################################################
#Section 6: List of valid abstract_port/input constraint generated from set_input_delay command.

• eg:abstract_port -ports "P2D_DB[0]" -clock "P2D_WRX"
• sdc：set_input_delay -max [expr $clk_period_wr * 0.6] -clock cc_mcu_wr {P2D_DCX}

########################################################################
#Section 7: List of valid output constraint generated from set_output_delay command.

• eg:output  -name "D2SRAM_SC_COL_R[2]"  -clock "A2D_SYS_CLK"

########################################################################
#Section 8: List of valid clock_sense constraint generated from set_clock_sense command.
#These constraint are generated only for -stop_propagtion in set_clock_sense.

########################################################################
#Section 9: List of valid cdc false path constraint generated from sdc command.
#These constraint are generated only for real clocks.

---

• sdc:set_clock_groups \ -logically_exclusive \-group {cc_mcu_wr mcu_spi_otp_clk} \ -group {cc_mcu_rd} \ -group {cc_osc_clk} \ -group {cc_clk_sys}
• set_false_path -from [get_ports A2D_LVD_VCI]
• set_false_path -to  [get_ports D2P_TESTO[3]]

三种类型set group 和set_false_path form**to**/set_false_

-----------------------------------------------------------------------------------------------------------------------------------

• skip_sgdc_sanity_start
• cdc_false_path -from cc_mcu_wr -from_type clock  -to cc_mcu_rd -to_type clock 
• cdc_false_path -from cc_mcu_rd -from_type clock  -to cc_mcu_wr -to_type clock 
• cdc_false_path -from cc_mcu_wr -from_type clock  -to cc_osc_clk -to_type clock 
• cdc_false_path -from cc_osc_clk -from_type clock  -to cc_mcu_wr -to_type clock 
• cdc_false_path -from cc_mcu_rd -from_type clock  -to cc_osc_clk -to_type clock 
• cdc_false_path -from cc_osc_clk -from_type clock  -to cc_mcu_rd -to_type clock 
• skip_sgdc_sanity_end

########################################################################
#Section 10: List of disable_timing constraint generated from set_disable_timing sdc command.
#These constraint are generated only for those sdc command which have object list as lib cells only.

########################################################################
#Section 11: List of valid false path constraint generated from sdc command.
#These constraint are generated only for real clocks.
#The type for constraint false_path is specified as below:
#        - scg_logically_exclusive: When it is translated from set_clock_group -logically_exclusive
#        - scg_physically_exclusive: When it is translated from set_clock_group -physically_exclusive
#        - scg_asynchronous: When it is translated from set_clock_group -asynchronous
#        - sfp: When it is translated from set_false_path

########################################################################
#Section 12: List of valid sg_multi_cycle constraint generated from sdc command.

########################################################################
#Section 13: List of valid set_lib_timing_mode constraint generated from set_mode sdc command.