write_project_tcl

write_project_tcl

在vivado控制台下，运行如下命令：

write_project_tcl -use_bd_files {dest_path/your_script.tcl}
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会看到：

INFO: [Vivado-projutils-15] 

Please note that by default, the file path for the project source files were set wth respect to the 'origin_dir' variable in the generated script.

When this script is executed from the output directory, these source files will be referenced with respect to this 'origin_dir' path value.
 
In case this script was later moved to a different directory, the 'origin_dir' value must be set manually in the script with the path relative to the new output directory to make sure that the source files are referenced correctly from the original project. 
 
You can also set the 'origin_dir' automatically by setting the 'origin_dir_loc' variable in the tcl shell before sourcing this generated script.
 
The 'origin_dir_loc' variable should be set to the path relative to the new output directory. 

Alternatively, if you are sourcing the script from the Vivado command line, then set the origin dir using '-tclargs --origin_dir '.
 
For example, 'vivado -mode tcl -source your_script.tcl -tclargs --origin_dir ".."'
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WARNING: [Vivado-projutils-10]

Found source(s) that were local or imported into the project.

If this project is being source controlled, then please ensure that the project source(s) are also part of this source controlled data. 

The list of these local source(s) can be found in the generated script under the header section.
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write_project_tcl生成的tcl文件，并非可以独立运行，还要依赖生成这个文件原来的文件。如果想通过tcl scripte来实现对vivado的版本控制，这样直接操作肯定不行。

不带use_bd_files，一样的提示。

write_project_tcl {dest_path/your_script.tcl}
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另外，

The list of these local source(s) can be found in the generated script under the header section.
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这句话肯定不对。实际上，这个tcl script要跑起来，不仅需要在头部注释里提到的几个文件。如果用到了block design, 那srcs里bd目录下的几乎所有的文件都要用到。

write_bd_tcl的bug

若是想把block design也用tcl script来生成，也会遇到问题。参考下面的链接：
https://support.xilinx.com/s/article/71497?language=en_US
write_bd_tcl writing out incorrect properties for AXI4-Stream IPs
DESCRIPTION
When I try to generate a block diagram from Tcl generated with write_bd_tcl, some AXI4-Stream IPs give the following error:

ERROR: [IP_Flow 19-3478] Validation failed for parameter ‘M13 TDATA Remap String(M13_TDATA_REMAP)’ with value ‘tdata[127:0]’ for BD Cell ‘axis_broadcaster_0’. Range specification exceeds input signal width (8): tdata[127:0],Error: element tdata[127:0] makes remap too large!
ERROR: [IP_Flow 19-3478] Validation failed for parameter ‘M14 TDATA Remap String(M14_TDATA_REMAP)’ with value ‘tdata[127:0]’ for BD Cell ‘axis_broadcaster_0’. Range specification exceeds input signal width (8): tdata[127:0],Error: element tdata[127:0] makes remap too large!

This issue has shown up with the AXI4-Stream Broadcaster IP and the AXI4-Stream Subset Converter IP.

SOLUTION
This issue occurs because write_bd_tcl does not output parameters that it detects as being set to default values.

To work around the issue, validate the original design and then set the S/M_TDATA_NUM_BYTES parameters from automatic to manual mode in the IP’s customization GUI.

This will direct IP Integrator to write out the CONFIG.S/M_TDATA_NUM_BYTES lines to the write_bd_tcl file.

解决办法就是使用write_bd_tcl或者write_project_tcl之前，将axi4-stream的ip里对于位宽的参数设置从auto设为manual模式。

另外，还会遇到问题：

WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/m00_regslice/m_axi_rid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/m00_regslice/m_axi_bid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
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推测，与上一条原因类似，id的位宽要从auto改为manual。