- class mcdf_bus_env extends uvm_env;
- mcdf_bus_agent agent;
- mcdf_rgm rgm;
- reg2mcdf_adapter reg2mcdf;
- uvm_reg_predictor #(mcdf_bus_trans) mcdf2reg_predictor;
- ...//注册+例化
- function void build_phase(u p);
- agent=mcdf_bus_agent::type_id::create("agent", this);
- if(!uvm_config_db#(mcdf_rgm)::get(this, "", "rgm", rgm)) begin
- `uvm_info()
- rgm=mcdf_rgm::type_id::create("", this);
- `uvm_info() end
- rgm.build();
- reg2mcdf=reg2mcdf_adapter::type_id::create("");
- mcdf2reg_predictor=uvm_reg_predictor#(mcdf_bus_trans)::type_id::create("", this);
- mcdf2reg_predictor.map=rgm.map;
- mcdf2reg_predictor.adapter=reg2mcdf;
- endfunction
- function void connect_phase(u p);
- rgm.map.set_sequencer(agent.sequencer, reg2mcdf);
- agent.monitor.ap.conncet(mcdf2reg_predictor.bus_in);
- endfunction
- endclass
针对reg对象,而不是reg block或者field

- @(negedge p_sequencer.vif.rstn);
- rgm.reset();//reg块的mv和dv复位
- rgm.chnl-_ctrl_reg.reset();//reg级别复位
- rgm.chnl0_ctrl_reg.pkt_len.reset();//reg域的复位
- rstval=rgm.chnl0_ctrl_reg.get_reset();//rgm的复位值,不是硬件的
- rgm.chnl0_ctrl_reg.read(status, data, UVM_BACKDOOR, .parent(this));
- if(rstval !=data) `uvm_error()
rgm.chnl0_ctrl_reg.mirror(status, UVM_CHECK, UVM_FRONTDOOR, .parent(this));
- void'(rgm.chnl0_ctrl_reg.randomize());
- rgm.chnl0_ctrl_reg.pkt_len.set('h3);
- rgm.chnl0_ctrl_reg.updata(statusm, UVM_FRONTDOOR, .parent(this));
- void'(rgm.chnl1_ctrl_reg.randomize());
- rgm.chnl0_ctrl_reg.set('h22);//1 or 0 ?
- rgm.updata(statusm, UVM_FRONTDOOR, .parent(this));

uvm针对寄存器模型内建的seq,建议在验证项目一开始先做检查
- class mcdf_example_seq extends uvm_reg_sequence;
- mcdf_rgm rgm;
- `uvm_object_utils()
- `uvm_declare_p_sequencer()
- ...
- task body();
- uvm_status_e status;
- uvm_reg_data_t data;
- uvm_reg_hw_reset_seq reg_rst_seq=new();
- uvm_reg_bit_bash_seq reg_bit_bas_seq=new();
- uvm_reg_access_seq reg_acc_seq=new();
- if(!uvm_config_db#(mcdf_rgm)::get(null, get_full_name(), "rgm", rgm)) begin
- `uvm_error() end
- @(negedge p_sequencer.vif.rstn);
- @(posedge p_sequencer.vif.rstn);
- `uvm_info()
- reg_rst_seq.model=rgm;
- reg_rst_seq.start(m_sequencer);
- `uvm_info()
- `uvm_info()
- reg_bit_bash_seq.model=rgm;
- reg_bit_bash_seq.start(m_sequencer);
- `uvm_info()
- `uvm_info()
- reg_acc_seq.model=rgm;
- reg_acc_seq.start(m_sequencer);
- `uvm_info()
- endtask
- endclass